Neuromorphic Edge Architecture for Running Event AI on Real Hardware
To process the spatiotemporal information generated by DVS Event Vision and SNN inside an autonomous mobile system, sensor input, event buffering, the SNN inference engine, memory, control processor, and external interfaces must operate as one integrated edge system.
Robowink’s Neuromorphic Edge Architecture research focuses not on re-explaining the algorithm itself, but on mapping trained SNN models to real hardware and jointly optimizing latency, memory, power, and interfaces.
From a hardware perspective, event-packet reception and buffering, SNN inference, system control, and external-device integration are separated into functional blocks while the architecture is designed to minimize data movement.
Parses the format of asynchronous events from DVS and external sensors and converts timestamps and address information into the internal data structure.
Buffers bursty event input and provides the data-movement path to memory and the inference engine.
Executes weight access, neuron-state updates, threshold comparison, and spike generation in dedicated hardware.
Handles register configuration, execution scheduling, error handling, mode control, and external-system commands.
Provides communication, status, and control interfaces for the robot controller and peripheral devices.
The research focuses on hardware that efficiently executes the recurring operations of SNN inference, including spike routing, weight access, membrane-potential accumulation, and firing, rather than on the learning algorithm itself.
Routes active events to the required neuron and synapse regions and manages processing order.
Studies local placement of trained weights to reduce external-memory access and data movement.
Stores neuron membrane potentials and internal states and updates them for each spike input.
Compares the accumulated state with the threshold and generates output spikes and reset operations.
The key to SNN edge hardware is not to run every compute block at maximum load continuously, but to regulate computation, memory access, and scheduling around active spikes and neurons.
Queues only the spikes that actually occur and manages their priority and processing order.
Selectively accesses only the memory regions required for active synapses and neuron states.
Keeps neuron states and intermediate results as close as possible to the compute blocks to reduce data movement.
Explores architectures that reduce block activity during idle periods and dynamically allocate execution resources according to event density.
SNN hardware performance depends not only on compute units but also on where weights and neuron states are placed and how often they are moved. We take a staged approach that separates current implementations from next-generation non-volatile-memory research.
For MPW and early SoC implementations, we examine architectures that place weights and neuron states primarily in on-chip SRAM and event buffers, which are easier to control and validate.
In the mid- to long-term research track, we extend the architecture toward neuromorphic systems that use non-volatile memory and Compute-in-Memory to further reduce data movement for weight storage and accumulation operations.
Deploying an SNN model to hardware requires the network structure, numerical precision, memory placement, registers, and drivers to be designed as one execution environment.
Maps SNN layers and neuron groups to accelerator resources and memory regions.
Adjusts the bit width of weights and state values to balance accuracy, memory use, and computational cost.
Defines the control interface that allows the RISC-V/MCU to configure and run the accelerator and read its status.
Provides a Runtime and SDK for model loading, execution-time measurement, and analysis of event and memory usage.
This staged research roadmap begins with an initial algorithm-validation environment, proceeds through FPGA/MPW-based hardware validation, and ultimately advances toward a dedicated architecture optimized for event-driven SNN computation.
First validates the functionality and data flow of DVS input and SNN algorithms on a general-purpose edge-computing platform.
Validates Event I/O, the SNN Accelerator, RISC-V/MCU, and memory architecture at the RTL/FPGA and MPW stages.
Extends toward a low-power neuromorphic SoC architecture combining SNN computation with non-volatile memory such as MRAM/ReRAM.
Evaluation focuses on data-processing efficiency and hardware-resource utilization on the actual execution platform.
The four Research pages describe different layers of a single technology stack rather than repeating the same content.
Studies acquisition, calibration, representation, and spatiotemporal preprocessing of brightness-change events.
Studies AI models that convert events into spikes and learn and infer temporal patterns.
Maps SNN models to dedicated accelerators, RISC-V/MCU, and memory architectures.
Aligns multiple sensors with mobility-state information and connects them to real system interfaces.
We welcome technical collaboration for SNN Accelerators, RISC-V/MCU SoCs, memory architectures, HW/SW co-design, and MPW implementation.
